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In an unprecedented display of urgency at a critical juncture in the history of the semiconductor industry, several of the largest organizations representing semiconductor design and manufacturing have announced initiatives to create industry standards defining 3D integrated circuits (3D IC) a technology that could solve key challenges to the continuation of Moore’s Law.
First, the Semiconductor Equipment and Materials Industry association (SEMI) said it has formed a Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee to explore standardization of this nascent chip stacking technology, which may be a key enabler of the continuation of Moore’s Law. Within a few hours, SEMATECH, the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC) released a similar announcement, saying they have established a new 3D Enablement program to drive industry standardization efforts and technical specifications for heterogeneous 3D integration.
All of these organizations appear to be working toward the same end but addressing slightly different aspects of the challenge. The effort required to make 3D ICs commercially viable in high volumes is expected to be huge, since it requires new approaches to almost every aspect of semiconductor design, manufacturing, inspection, test and handling. Faults at any step in the process could result in a multiplicative effect, increasing the odds of failure of the end product. This challenge is complicated by the variety of design and engineering alternatives that have been proposed to date.
“The lack of convergence will delay industry success” said Larry W. Sumney, president and CEO of SRC, adding that, “We will pursue an ambitious interface standardization for 3D integration to enable the commercialization of 3D ICs.”
Indeed, semiconductor foundry giant TSMC said in July that it intends to begin commercial production of 3D ICs in 2012, which would require a significant acceleration of activity by many of its vendors.
The new 3D Enablement program, launched by a group of existing member companies in SIA and SEMATECH, will focus primarily on developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. To achieve this SEMATECH will partner with SRC to enable select university research projects.
The program will be administered by SEMATECH’s 3D Interconnect program, based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, and working in partnership with SRC, the program aims to establish the infrastructure necessary for the industry to leverage 3D packaging technology for new applications.
“The semiconductor industry, specifically the development of 3D integration, is at an inflection point,” said Dr. John E. Kelly III, senior vice president and director of research at IBM and chair of SIA’s technology steering committee. “In tackling the challenges faced by lack of standardization, we will have deep collaboration with SEMATECH and SRC addressing both bonding processes and 3D inspection. The program will accelerate the adoption of 3D integration technology.”
3D stacked integrated circuits are composed of a stack of two-dimensional die, and are viewed as critical in helping the semiconductor industry keep pace with rigorous performance demands in the face of severe chip density, timing and power challenges. But the challenges are huge, as each die in the stack could comprise a completely different set of functions. For example, the top die could be an image sensor, the middle die could be a system-on-chip with multiple processors and communications cores, and the bottom die could be a state-of-the-art memory chip. The semiconductor industry has never had a standardized design modality that enables this degree of integration in three dimensions, although commercial proposals have been put forth by Cadence Design Systems and others.
While technologies for closely connecting chips have existed for a while, in the form of wirebonding and flip-chip packages, next-generation of 3D integration allows manufacturers to directly sandwich chips together using through-silicon via (TSV) technology as the primary method of interconnect between the die. While there are many ways of accomplishing this, and TSVs are one of the most rapidly developing technologies in the semiconductor industry, cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed, said SEMI representatives.
3DS-ICs promise a fundamental shift for current multi-chip integration and packaging approaches. 3DS-ICs are already in production for CMOS image sensors, and high-volume manufacturing of some memory devices is expected in 2013. Widespread use of 3DS-ICs would result in increased performance, smaller footprints, and reduced cost and power consumption. However, multiple manufacturing challenges must first be solved because 3DS-ICs’ increased design and mechanical complexity can lead to signal interference, increased manufacturing defects, and thermal management issues.
Companies supporting the formation of a SEMI 3DS-IC Standards Committee include: Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron, and Xilinx. Other companies involved in 3D IC standardization include GLOBALFOUNDRIES, HP, IBM, Intel, Samsung, and UMC.
Just recently, SEMI and SEMATECH organized advanced workshops on the subject, including major companies such as TSMC, UMC, Amkor, ASE, Samsung, Qualcomm, ITRI, IMEC, Applied Materials, Novellus, KLA-Tencor, Brewer Science and 3M. Semiconductor design software companies who have been publicly working on the challenge include Apache, Atrenta, Cadence Design Systems and Mentor Graphics, while another standards body, Si2, said it has been working on 3D IC standards earlier this year. A variety of smaller but no less innovative companies, such as SanDisk, Tezzaron, Ziptronics and ZyCube are also working on novel 3D approaches.